An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders

This paper presents a novel area-efficient truncated inversionless Berlekamp-Massey (TiBM) architecture for Reed- Solomon decoders. Especially this paper proposes how to truncate processing elements (PE) in order to reduce the hardware complexity of key equation solver (KES) block. The RS decoder using proposed TiBM architecture has been designed and implemented by 90-nm CMOS standard cell technology with a supply voltage of 1.1 V. The RS decoder using proposed TiBM architecture operates at a clock frequency of 400 MHz and has a throughput of 3.2 Gb/s. The proposed architecture requires approximately 25.4% fewer gate counts than architecture based on the conventional RiBM algorithm.