Title :
Design and implementation of two variable multiplier using KCM and Vedic Mathematics
Author :
Sriraman, L. ; Prabakar, T.N.
Author_Institution :
Dept. of ECE, Oxford Eng. Coll., Trichy, India
Abstract :
In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier´s architecture is similar to that of a Constant Co-efficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava Multiplier for both 8 bit and 16 bit cases and the results are presented. The proposed multiplier is 1.5 times faster than the other multipliers for 16×16 case and consumes only 76% area for 8×8 multiplier and 42% area for 16×16 multiplier.
Keywords :
field programmable gate arrays; logic design; multiplying circuits; Cyclone III FPGA; KCM; ROM approach; Urdhava multiplier; Vedic mathematics; array multiplier; constant co-efficient multiplier; multiplier architecture; two variable multiplier; word length 16 bit; word length 8 bit; Arrays; Field programmable gate arrays; Logic gates; Registers; Array Multiplier; FPGA; KCM; Urdhava; Vedic Maths;
Conference_Titel :
Recent Advances in Information Technology (RAIT), 2012 1st International Conference on
Conference_Location :
Dhanbad
Print_ISBN :
978-1-4577-0694-3
DOI :
10.1109/RAIT.2012.6194554
