• DocumentCode
    1999396
  • Title

    A 2.0 V, 0.35 /spl mu/m partially depleted SOI-CMOS technology

  • Author

    Mistry, K. ; Grula, G. ; Sleight, J. ; Bai, Lin ; Stephany, R. ; Flatley, R. ; Skerry, P.

  • Author_Institution
    Digital Equipment Corp., Hudson, MA, USA
  • fYear
    1997
  • fDate
    10-10 Dec. 1997
  • Firstpage
    583
  • Lastpage
    586
  • Abstract
    A 0.35 /spl mu/m SOI CMOS technology has been demonstrated with excellent partially depleted device characteristics, minimal floating body effects, a unique Schottky body tie scheme, and 1 M SRAM yield approaching bulk CMOS. A state-of-the-art microprocessor fabricated on SOI showed greater than 20% performance improvement over bulk CMOS at the same VDD, or 50% reduction in power dissipation at the same operating frequency.
  • Keywords
    silicon-on-insulator; 0.35 micron; 1 Mbit; 2 V; SRAM yield; Schottky body tie scheme; Si; floating body effects; microprocessor; partially depleted SOI-CMOS technology; partially depleted device characteristics; submicron process; CMOS technology; Degradation; Delay; Hysteresis; MOSFET circuits; Microprocessors; Power dissipation; Pulse measurements; Random access memory; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-4100-7
  • Type

    conf

  • DOI
    10.1109/IEDM.1997.650452
  • Filename
    650452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1999396