Scalability of partially depleted SOI technology for sub-0.25 /spl mu/m logic applications

Author

Chau, R. ; Arghavani, R. ; Alavi, Meysam ; Douglas, Deborah ; Green, Ron ; Tyagi, Swati ; Xu, Jie ; Packan, P. ; Yu, Son-Cheol ; Chunlin Liang

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

591

Lastpage

594

Abstract

The scalability of partially depleted (PD) SOI with a floating body has been evaluated to below the sub-0.25 /spl mu/m regime using transistors, ring oscillators and 4 Mb SRAMs as test vehicles. In this paper the speed and power performance of PD-SOI are compared to those of bulk for 1.8 V/sub-0.25 /spl mu/m logic applications. In addition, the 4 Mb SOI SRAM yield issues are revealed. Using the same transistor off-state leakage current limit criterion for both bulk and SOI, we conclude that PD-SOI with a floating body will provide no speed and insignificant power advantage over bulk for sub-0.25 /spl mu/m logic applications.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; integrated circuit technology; integrated circuit yield; silicon-on-insulator; 0.25 micron; 4 Mbit; SOI SRAM yield; Si; floating body; partially depleted SOI technology; power performance; ring oscillators; scalability; submicron logic applications; transistor offstate leakage current limit criterion; Analytical models; Capacitance; Delay; Integrated circuit interconnections; Logic; Random access memory; Ring oscillators; Scalability; Testing; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650454

Filename

650454