Advanced 0.5 /spl mu/m FRAM device technology with full compatibility of half-micron CMOS logic device

Author

Yamazaki, T. ; Inoue, K.-i. ; Miyazawa, H. ; Nakamura, M. ; Sashida, N. ; Satomi, R. ; Kerry, A. ; Katoh, Y. ; Noshiro, H. ; Takai, K. ; Shinohara, R. ; Ohno, C. ; Nakajima, T. ; Furumura, Y. ; Kawamura, S.

Author_Institution

Adv. Process Integration Dept., Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

613

Lastpage

616

Abstract

We developed the 1T/1C FRAM device technology using 0.5 /spl mu/m design rule which is perfectly compatible with 0.5 /spl mu/m CMOS logic process. This technology achieves the small 1T/1C FRAM cell size of 12.5 /spl mu/m/sup 2/, and minimized process degradations of ferroelectric material characteristics using low-power inter layer dielectric film deposition technique. Using this technology, we successfully integrated the 68 kbit-FRAM and 8 bit-MCU.

Keywords

CMOS logic circuits; ferroelectric storage; random-access storage; 0.5 micron; 1T/1C FRAM device technology; 68 kbit; 8 bit; CMOS logic device; MCU; ferroelectric nonvolatile memory; low-power inter layer dielectric film deposition; CMOS logic circuits; CMOS process; CMOS technology; Degradation; Ferroelectric films; Ferroelectric materials; Logic design; Logic devices; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650459

Filename

650459