Title :
A 5 GHz low-power, high-linearity low-noise amplifier in a digital 0.35 μm CMOS process
Author :
Fairbanks, John S. ; Larson, Lawrence E.
Author_Institution :
Center for Wireless Commun., California Univ., La Jolla, CA, USA
Abstract :
A 5 GHz low noise amplifier (LNA), intended for use in a wireless local area network (WLAN) receiver, has been implemented in a standard digital 0.35 μm CMOS process. The amplifier provides a power gain of 9.0 dB while consuming 11 mW from a 2.2 V supply and reaches 6.0 dBm at third order input intermodulation intercept point (IIIP3). In this paper, we present a brief analysis of the LNA architecture and experimental results.
Keywords :
CMOS digital integrated circuits; integrated circuit noise; optimisation; radio receivers; radiofrequency amplifiers; radiofrequency integrated circuits; wireless LAN; 11 mW; 2.2 V; 5 GHz; 9 dB; WLAN; input intermodulation intercept point; low-noise amplifier; standard digital CMOS process; wireless local area network receiver; Bandwidth; CMOS process; CMOS technology; Linearity; Low-noise amplifiers; MOSFET circuits; Noise figure; Noise measurement; Radio frequency; Radiofrequency amplifiers;
Conference_Titel :
Radio and Wireless Conference, 2003. RAWCON '03. Proceedings
Print_ISBN :
0-7803-7829-6
DOI :
10.1109/RAWCON.2003.1227968
