Effect of technology scale-down on power reduction strategies

This paper presents limiting effect analysis of voltage scaling on Static Random Access Memory (SRAM) with process technology. The power reduction strategy utilize the property of standby circuit power reduction by reducing voltage swing available to cell by replacing ground and supply nodes by virtual ground and virtual supply nodes respectively. Important precaution to be taken in this method is complete charge removal from virtual nodes before next operation. Focus of this work is on the SRAM cell in 45nm and 32nm technology. Relative reduction in power is evaluated in context of process technology scale down. Cell behavior indicates process technology based design application of virtual supply and ground node technique. Power reduction by virtual ground node gives excellent response in 65nm and higher process technology but it ceases its impact as technology scales down beyond 45nm and 32nm. A detail comparative analysis of these two types of circuit arrangements for standby power reduction of SRAM with changing operating condition has been carried out in 32nm, 45nm.65nm, 90nm and 120nm.