Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing

Because of the delay of next generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20nm technology nodes. For advanced sub-10nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning (SAOP) will be required. Due to considerable design complexity and unmanageable process variation, one-dimensional grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable because cut mask rules are limited by conventional 193nm lithography. To the best of our knowledge, existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and post-layout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks.