DocumentCode
2000141
Title
A bit-write reduction method based on error-correcting codes for non-volatile memories
Author
Tawada, Masashi ; Kimura, Shinji ; Yanagisawa, Masao ; Togawa, Nozomu
Author_Institution
Dept. of Comput. Sci. & Eng., Waseda Univ., Tokyo, Japan
fYear
2015
fDate
19-22 Jan. 2015
Firstpage
496
Lastpage
501
Abstract
Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.
Keywords
error correction codes; random-access storage; bit write reduction; error correcting codes; flipped bits; information vector; memory cell; nonvolatile memory; write reduction codes; write reduction codewords; writing bits; Computer architecture; Encoding; Error correction codes; Microprocessors; Nonvolatile memory; Vectors; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
978-1-4799-7790-1
Type
conf
DOI
10.1109/ASPDAC.2015.7059055
Filename
7059055
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