Frequency Limitation by Interconnecting Lines in Wafer Scale Integration Circuits

Propagation mechanism in Wafer Scale Integration (WSI) interconnection lines is more complex than in lines deposited on insulating substrates (like GaAs). The dielectric being multilayered (Air - SiO2 - Si), the propagating modes are hybrid. The properties of these modes are related to the frequency of propagated signals and the silicon conductivity. An electromagnetic analysis based upon the Spectral Domain Approach (SDA) allows to determine the propagation exponent vesus frequency for various substrate conductivities; dissipative and dispersive effects involved by silicon losses are pointed out. An equivalent scheme of the interconnect is derived from this analysis. It is used in a custom dynamic simulation program to calculate the time domain response of the interconnect to fast logic signals. The simulation results show that the propagating signal are delayed and distorded. The delay time (td) and the rise time (tr) can be calculated by the simple relations: td (pS) ¿ 85 l(cm) and tr (pS) ¿ 200 12 (cm). In WSI circuits, where interconnects may reach 10 cm long, these effects reduce drastically the clock frequency Fc of the circuit (Fc < 25 MHz), and consequently the performance of the system.