Title :
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST
Author :
Liang-Che Li ; Wen-Hsuan Hsu ; Kuen-Jong Lee ; Chun-Lung Hsu
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.
Keywords :
built-in self test; fault diagnosis; integrated circuit testing; integrated logic circuits; integrated memory circuits; three-dimensional integrated circuits; efficient 3D IC on-chip test framework; embed TSV testing; fault diagnosis; memory BIST process; memory-logic stacked IC; test patterns; Built-in self-test; Delays; Memory management; Registers; Through-silicon vias; Watches; 3D-IC; Memory BIST; TSV testing;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
DOI :
10.1109/ASPDAC.2015.7059059
