Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM

Modern CMOS technology enables the integration of billions of transistors on a single chip. Emerging three-dimensional (3D) stacking techniques using through-silicon vias (TSVs) promise even higher integration by combining multiple dies in a single package. In order to keep the test cost low and enhance field reliability, there is a need to re-think conventional test practices, such as test-data compression and online testing, as well as test-application techniques and fault diagnosis. Traditional hardware-based on-chip decompression solutions are limited to compression techniques that do not require large hardware overhead for decompression. However, today´s system-on-chip designs (SoCs) offer resources, such as embedded processors and large amounts of fast embedded memories, that can be exploited for efficient on-chip test application, online testing, and diagnosis using software-based compression. Examples of such systems are 3D ICs with wide-I/O DRAM or traditional ICs with embedded DRAM (eDRAM). We propose a test and diagnosis solution that makes use of software-based decompression of deterministic scan-test pattern and allows for test application from on-chip DRAM to the logic die, extending traditional hardware-based methods and allowing for online scan-based test and diagnosis. This solution therefore targets SoCs that contain, in addition to a microprocessor, multiple digital-logic cores and glue logic, all of which need to be tested using scan test patterns. Simulation results for benchmarks show that we can achieve high test-data compression, comparable with what is obtained using commercial tools, as well as high-resolution on-chip diagnosis with negligible hardware and test-time overhead.