• DocumentCode
    2000472
  • Title

    Modeling and design optimization of ReRAM

  • Author

    Kang, J.F. ; Li, H.T. ; Huang, P. ; Chen, Z. ; Gao, B. ; Liu, X.Y. ; Jiang, Z.Z. ; Wong, H.-S.P.

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • fYear
    2015
  • fDate
    19-22 Jan. 2015
  • Firstpage
    576
  • Lastpage
    581
  • Abstract
    Resistive switching memories (ReRAM) have been widely studied for applications in next-generation data storage and neurormorphic computing systems. To enable device-circuit-system co-design and optimization, a SPICE model of ReRAM that can reproduce the device characteristics in circuit simulations is needed. In this paper, we present a novel tool for ReRAM design including a physics-based SPICE model, the model parameters extraction strategy, as well as the system assessment method. This physics-based SPICE model can capture all the essential features of HfOx-based ReRAM including the DC/AC and multi-level switching behaviors, switching reliability, and intrinsic device variations. A strategy is developed to extract the critical model parameters from the fabricated ReRAM devices. A variety of electrical measurements on various ReRAMs are performed to verify and calibrate the model. The assessment method based on the experimentally verified SPICE model can be applied to explore a wide range of applications including: 1) variation-aware and reliability-emphasized system design; 2) system performance evaluation; 3) array architecture optimization. This verified design tool not only enables system design but also enables system optimization that capitalizes on device/circuit interaction for both data storage and neuromorphic computing applications.
  • Keywords
    SPICE; circuit optimisation; circuit simulation; hafnium compounds; high-k dielectric thin films; integrated circuit design; integrated circuit modelling; integrated circuit reliability; resistive RAM; DC/AC behaviors; HfOx; ReRAM design optimization; ReRAM modelling; array architecture optimization; circuit simulations; device characteristics; device-circuit-system co-design; electrical measurements; intrinsic device variations; model parameter extraction strategy; multilevel switching behaviors; neurormorphic computing systems; next-generation data storage; physics-based SPICE model; reliability-emphasized system design; resistive switching memories; switching reliability; system assessment method; system performance evaluation; variation-aware system design; Arrays; Current measurement; Reliability; Resistance; SPICE; Switches; Voltage measurement; SPICE model; emerging memory; resistive switching memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    978-1-4799-7790-1
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2015.7059070
  • Filename
    7059070