Author :
Venkatesan, S. ; Gelatos, A.V. ; Hisra, S. ; Smith, B. ; Islam, R. ; Cope, J. ; Wilson, B. ; Tuttle, D. ; Cardwell, R. ; Anderson, S. ; Angyal, M. ; Bajaj, R. ; Capasso, C. ; Crabtree, P. ; Das, S. ; Farkas, J. ; Filipiak, S. ; Fiordalice, B. ; Freeman, M
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
Abstract :
A high performance 0.20 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15/spl plusmn/0.04 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized and enable fabrication of 7.6 /spl mu/m/sup 2/ 6T SRAM cells.
Keywords :
CMOS logic circuits; copper; integrated circuit interconnections; integrated circuit metallisation; 0.15 micron; 0.2 micron; 1.8 V; 6T SRAM cells; CMOS technology; Cu; Cu metallization; high performance logic technology; low power-delay products; low resistance interconnects; planarized Cu interconnects; reliability; CMOS technology; Copper; Delay; Doping; Hot carriers; Implants; MOS devices; MOSFETs; Metallization; Thermal stresses;
