A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

Author

Washio, K. ; Ohue, E. ; Oda, K. ; Tanabe, M. ; Shimamoto, H. ; Onai, T.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

795

Lastpage

798

Abstract

A selective-epitaxial SiGe base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/IDP (SMI) electrodes is proposed. The SiGe-base structure, self-aligned to the 0.1-/spl mu/m-wide emitter, effectively reduces collector capacitance and SMI electrodes provide low parasitic resistances. A BPSG/SiO/sub 2/-refilled trench was introduced to reduce the substrate capacitance. A 9.3-ps delay time in a differential ECL ring oscillator was achieved.

Keywords

Ge-Si alloys; delays; emitter-coupled logic; heterojunction bipolar transistors; semiconductor device metallisation; semiconductor epitaxial layers; semiconductor materials; 9.3 ps; BPSG/SiO/sub 2/-refilled trench; SMI electrode; SiGe; collector capacitance; differential ECL ring oscillator; gate delay; heterojunction bipolar transistor; parasitic resistance; selective-epitaxial SiGe HBT; self-aligned stacked metal/IDP; substrate capacitance; Bipolar transistors; Delay effects; Electrodes; Germanium silicon alloys; Heterojunction bipolar transistors; Millimeter wave technology; Parasitic capacitance; Silicon germanium; Substrates; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650501

Filename

650501