System-level design verification in the AT&T computer division: overview and strategy

The authors present the experience and strategy guiding the system-level computer-aided design verification (CADV) process used in the AT&T computer division. Specifically, they provide an overview of processes, results, and the strategy used to choose among modeling options, styles for the verification process, methods for test development, timing models, and techniques for analyzing results. CADV is now being used on ten active projects. The use of CADV has reduced the number of circuit board artmaster cycles required to produce a high-quality design for high-volume manufacture from an average of 3.5 to 4 cycles to an average of 2 cycles