Battery-aware mapping optimization of loop nests for CGRAs

Coarse-grained Reconfigurable Architecture (CGRA) is a promising mobile computing platform that provides both high performance and high energy efficiency. Since loop nests are usually mapped onto CGRA for acceleration, optimizing the mapping is an important goal for design of CGRAs. Moreover, how to reduce energy consumption also becomes one of primary concerns in using CGRAs. This paper makes three contributions: a) Proposing an energy consumption model for CGRA; b) Formulating loop nests mapping problem to minimize the battery charge loss; c) Extract an efficient heuristic algorithm called BPMap. Experiment results show that our methods improve the performance of the kernels and lower the energy consumption.