Evaluation of circuit reliability based on distribution of different signal input patterns

As digital logic circuit are being fabricated at nanometer scale, the reliability of the circuit becomes an important issue. Therefore the reliability modeling is increasingly important subject to be considered in designing modern logic integrated circuits at submicron level. This drives a need to compute reliability measure for nano-scale circuits. Two main reliability measuring tools used commonly in the literature are e.g. Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) other than Probabilistic Transfer Matrix (PTM). Here, the research work is constrained to PGM and BDEC models only as PTM model consume higher execution time and memory usage. This paper looks into the accuracy of circuit´s reliability evaluation by BDEC compared to control reliability evaluation method, PGM. Both models are able to estimate circuit´s reliability in the presence of soft errors. It is shown that BDEC model gives higher reliability values compared to PGM model for a set of circuits with same functionality but as the complexity of the circuits and the gate error values increases, BDEC tend to be inferior compared to PGM. This occurrence is explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure for BDEC depends on the circuit design (though with same functionality), gate error and probability of the input signal, being one or zero.