• DocumentCode
    2001245
  • Title

    Tolerating Dependences Between Large Speculative Threads Via Sub-Threads

  • Author

    Colohan, Christopher B. ; Ailamaki, Anastassia ; Steffan, J. Gregory ; Mowry, Todd C.

  • Author_Institution
    Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    216
  • Lastpage
    226
  • Abstract
    Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range in size from hundreds to several thousand dynamic instructions and have minimal dependences between them. Recent work has shown that TLS can offer compelling performance improvements for database workloads, but only when targeting much larger speculative threads of more than 50,000 dynamic instructions per thread, with many frequent data dependences between them. To support such large and dependent speculative threads, hardware must be able to buffer the additional speculative state, and must also address the more challenging problem of tolerating the resulting cross-thread data dependences. In this paper we present hardware support for large speculative threads that integrates several previous proposals for TLS hardware. We also introduce support for sub-threads; a mechanism for tolerating cross-thread data dependences by checkpointing speculative execution. When speculation fails due to a violated data dependence, with sub-threads the failed thread need only rewind to the checkpoint of the appropriate sub-thread rather than rewinding to the start of execution; this significantly reduces the cost of mis-speculation. We evaluate our hardware support for large and dependent speculative threads in the database domain and find that the transaction response time for three of the five transactions from TPC-C (on a simulated 4-processor chip-multiprocessor) speedup by a factor of 1.9 to 2.9
  • Keywords
    checkpointing; multi-threading; parallel architectures; transaction processing; TLS hardware; TPC-C; checkpointing speculative execution; cross-thread data dependences; database workloads; frequent data dependences; speculative threads; subthreads; thread-level speculation; transaction response time; Checkpointing; Computer aided instruction; Computer science; Concurrent computing; Delay; Hardware; Parallel processing; Proposals; Transaction databases; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2006. ISCA '06. 33rd International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-2608-X
  • Type

    conf

  • DOI
    10.1109/ISCA.2006.43
  • Filename
    1635954