A “smart” switch based three-phase ZVS PWM topology

Soft switching conditions, namely zero-voltage switching (ZVS), for medium power high-frequency inverters are becoming of great interest. In this paper, a complete analysis and design procedure of a simple DC bus commutating subcircuit is discussed. The “smart” switch in combination with a DC bus capacitor provides the zero-volts interval across the inverter DC bus only when needed and in synchronisation with the pulsewidth modulation strategy. Another advantage includes no significant overvoltage across the inverter switches since the output load inductance and no other added one is used to achieve ZVS. Key theoretical results are extensively verified by simulation