Title :
Pulse width constraints on RAMs for realizing fault-tolerant ASCs
Author :
Goel, A.K. ; Kalia, A.
Author_Institution :
Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
Abstract :
A simple and efficient method to realize ASCs (asynchronous sequential circuits) with the help of RAMs is developed. This method involves measurements on a particular class of ICs as a whole, and no measurements are required on individual RAMs before they are used to implement ASCs. In addition, arbitrary state assignments can be used, and no external delay elements are required. This reduces the design cost, and hence the cost of implementation, of the ASC
Keywords :
asynchronous sequential logic; circuit reliability; fault tolerant computing; integrated logic circuits; logic design; random-access storage; RAM pulse width constraints; arbitrary state assignments; asynchronous sequential circuits; fault-tolerant; logic IC; Clocks; Delay; Fault tolerance; Hazards; Pulse circuits; Read-write memory; Semiconductor memory; Sequential circuits; Space vector pulse width modulation; Timing;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.102082
