Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution

This paper addresses the verification of a modern multi-core SoC using an approach that quantifies the verification problem and defines its solution. We show how to analyze a specification to create a verification plan that describes the verification problem, quantifies it using measurable metrics, specifies the solution to the problem, and facilitates automation of functional closure. Specifically, we show how to analyze a specification with an eye toward identifying product features and their associated attributes and behavioral requirements. Quantifying the verification problem through coverage model design is demystified. We describe how to choose the appropriate verification technique-ex. simulation, formal, hybrid-for each feature and design its application. Finally, the use of verification plan automation, allowing the verification plan to be used to directly control and measure the verification process, is addressed. This paper is based on a tutorial having the same title given by the authors at the 2008 Multiprocessor Test and Verification (MTV) workshop.