BackSpace: Moving Towards Reality

Author

de Paula, Flavio M ; Gort, Marcel ; Hu, Alan J. ; Wilton, Steven J E

Author_Institution

Dept. of Comput. Sci., Univ. of British Columbia, Vancouver, BC

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

49

Lastpage

54

Abstract

In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some on-chip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles.

Keywords

computer debugging; field programmable gate arrays; microprocessor chips; BackSpace; FPGA; field programmable gate arrays; formal analysis; on-chip hardware; post-silicon debugging; Circuit testing; Computer crashes; Debugging; Formal verification; Hardware; Job shop scheduling; Monitoring; Observability; Silicon; Vehicle crash testing; Design-for-Debug; Formal Verification; Post-Silicon Debug;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification, 2008. MTV '08. Ninth International Workshop on

Conference_Location

Austin, TX

ISSN

1550-4093

Print_ISBN

978-1-4244-3682-8

Type

conf

DOI

10.1109/MTV.2008.22

Filename

5070934