• DocumentCode
    2003064
  • Title

    Influence Of Well Profile And Gate Length On The ESD Performance Of A Fully Silicided 0.25/spl mu/m Cmos Technology

  • Author

    Bock, K. ; Russ, C. ; Badenes, G. ; Groeseneken, G. ; Deferm, L.

  • Author_Institution
    Imec, Kapeldreef 75, B-3001 Leuven, Belgium,
  • fYear
    1997
  • fDate
    25-25 Sept. 1997
  • Firstpage
    308
  • Lastpage
    315
  • Keywords
    Breakdown voltage; CMOS process; CMOS technology; Degradation; Electrostatic discharge; Implants; Protection; Silicidation; Silicides; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium,1997. Proceedings
  • Conference_Location
    Orlando, FL, USA
  • Print_ISBN
    1-878303-69-4
  • Type

    conf

  • DOI
    10.1109/EOSESD.1997.634258
  • Filename
    634258
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2003064