Title :
Network Properties and Latency of Triple-based Hierarchical Interconnection Netrwork
Author :
Qiao, Baojun ; Shi, Feng ; Ji, Weizing ; Song, Hong
Author_Institution :
Beijing Inst. of Technol., Beijing
fDate :
May 30 2007-June 1 2007
Abstract :
A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC (System-on-Chip). Triple-based Hierarchical Interconnection Network (THIN) was proposed that aims to decrease the node degree, reduce the links and shorten the diameter. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. In this paper, the network properties and zero-load latency are studied and compared with 2-D mesh. The compare results show that THIN is a better candidate for constructing the NOC than 2-D Mesh, when there are not too many nodes.
Keywords :
hierarchical systems; multiprocessor interconnection networks; network-on-chip; 2D mesh; network latency; network-on-chip; system-on-chip; triple-based hierarchical interconnection network; zero-load latency; Automatic control; Bandwidth; Chip scale packaging; Computer science; Control systems; Delay; Multiprocessor interconnection networks; Network topology; Network-on-a-chip; System-on-a-chip; interconnection architecture; network properties; network topology; network-on-chip;
Conference_Titel :
Control and Automation, 2007. ICCA 2007. IEEE International Conference on
Conference_Location :
Guangzhou
Print_ISBN :
978-1-4244-0818-4
Electronic_ISBN :
978-1-4244-0818-4
DOI :
10.1109/ICCA.2007.4376501
