Title :
Design of SEU-hardened CMOS memory cells: the HIT cell
Author :
Bessot, D. ; Velazco, R.
Author_Institution :
Lab. de Genie Inf., IMAG, Grenoble, France
Abstract :
A memory cell, called HIT cell (heavy ion tolerant cell), designed to be SEU-immune is presented. Compared to previously reported design hardened solutions, the HIT cell is less SEU-sensitive, features better electrical performances and consumes less silicon area
Keywords :
CMOS integrated circuits; SRAM chips; ion beam effects; radiation hardening (electronics); HIT cell; SEU-hardened CMOS memory cells; SEU-immune; SEU-sensitive; design hardened solutions; electrical performances; heavy ion tolerant cell; silicon area; single event upset; Circuits; Land surface temperature; Latches; Manufacturing processes; Random access memory; Read-write memory; Resistors; Silicon; Single event transient; Single event upset;
Conference_Titel :
Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on
Conference_Location :
St. Malo
Print_ISBN :
0-7803-1793-9
DOI :
10.1109/RADECS.1993.316519
