SEU error rates in advanced digital CMOS

Single-event error rate analysis of radiation-hardened CMOS memory parts is presented. The statistical distribution on device processing parameters is shown to explain the non-ideal error cross-section data observed in contemporary six-transistor SRAMs designed for space-based operation. A procedure for evaluating the expected error rate for these parts is presented and applied to a typical data set. The method, which arises from a development of the upset rate convolution integral, can be applied in a generic fashion using conventional ground-based test data to provide a realistic upset-rate estimate for space flight conditions