Title :
Optimizing low side gate resistance for damping phase node ringing of synchronous buck converter
Author :
Zhiyang Chen ; Amaro, I.
Abstract :
This paper presents a method to optimize gate resistance of low side MOSFET in terms of damping phase node ringing for high efficiency synchronous buck converter. This method analyzes damping effect of low side gate resistance in the network of parasitic capacitances of MOSFET die and parasitic inductances of MOSFET package. Optimization equations for low side gate resistance are derived based on parasitic inductances and capacitances. Experiment proves the validity of this optimization design for low side gate resistance.
Keywords :
MOSFET; damping; optimisation; power convertors; damping phase node ringing; high efficiency synchronous buck converter; low side MOSFET; low side gate resistance; optimization equation; parasitic capacitances; parasitic inductances; Capacitance; Damping; Equations; Inductance; Logic gates; MOSFET circuits; Resistance;
Conference_Titel :
Energy Conversion Congress and Exposition (ECCE), 2012 IEEE
Conference_Location :
Raleigh, NC
Print_ISBN :
978-1-4673-0802-1
Electronic_ISBN :
978-1-4673-0801-4
DOI :
10.1109/ECCE.2012.6342590
