Variants of the Winograd multiplicative FFT algorithms and their implementation on IBM RS/6000

Variants of the Winograd (1976, 1980) multiplicative FFT (fast Fourier transform) algorithm for transform sizes of primes and product of primes are derived, which take advantage of a computer architecture with a multiply-add feature. For processors which perform floating-point addition, floating-point multiplication, and the floating-point multiply-add in one computer clock cycle, FFT algorithms can be designed such that all the floating-point multiplications can be overlapped by using multiply-adds. Implementation of multiply-add algorithms on an IBM RS/6000 is discussed. The use of a tensor product formulation throughout gives a means for producing variants of algorithms matching computer architectures