An SDRAM interface for simplified “at-speed” testing of the SLDRAM internal array

This paper outlines the SLDRAM interface and the functional architecture of a first generation SLDRAM device. We also discuss the means of testing and characterizing the DRAM array without the costs of using high speed testers for the entire test and characterization program. We present the work done to introduce an SDRAM-like test interface to the SLDRAM part, the merits, and the cost in die area. Also discussed are the use of on-chip data compression to reduce test complexity