DocumentCode :
2003454
Title :
An SDRAM interface for simplified “at-speed” testing of the SLDRAM internal array
Author :
Wu, John ; Paris, Lluis ; Stender, Jorg ; Harrison, Ian ; DeMone, Paul ; Millar, Bruce ; Benzreba, Jamal ; Gillingham, Peter
Author_Institution :
MOSAID Technols. Inc., Canada
fYear :
1998
fDate :
24-25 Aug 1998
Firstpage :
38
Lastpage :
44
Abstract :
This paper outlines the SLDRAM interface and the functional architecture of a first generation SLDRAM device. We also discuss the means of testing and characterizing the DRAM array without the costs of using high speed testers for the entire test and characterization program. We present the work done to introduce an SDRAM-like test interface to the SLDRAM part, the merits, and the cost in die area. Also discussed are the use of on-chip data compression to reduce test complexity
Keywords :
DRAM chips; cellular arrays; data compression; integrated circuit testing; memory architecture; SDRAM interface; SLDRAM internal array; at-speed testing; die area; functional architecture; on-chip data compression; test complexity; test interface; Bandwidth; Clocks; Computer aided manufacturing; Costs; DRAM chips; Data compression; Random access memory; SDRAM; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8494-1
Type :
conf
DOI :
10.1109/MTDT.1998.705944
Filename :
705944
Link To Document :
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