A VHDL core for intrinsic evolution of discrete time filters with signal feedback

Author

Gwaltney, David A. ; Dutton, Kenneth

Author_Institution

NASA Marshall Space Flight Center, Huntsville, AL, USA

fYear

2005

fDate

29 June-1 July 2005

Firstpage

43

Lastpage

50

Abstract

The design of an evolvable machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a digital signal processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a filter. The robustness of the evolved filter design is tested and its unique characteristics are described.

Keywords

IIR filters; digital signal processing chips; discrete time filters; evolutionary computation; feedback; firmware; hardware description languages; FPGA; IIR filter; VHDL core; control system applications; digital signal processor; discrete time filters; evolutionary algorithm; evolvable machine; evolvable system platform; signal feedback; Control systems; Digital signal processing; Digital signal processors; Evolutionary computation; Feedback; Field programmable gate arrays; IIR filters; Microprogramming; Robustness; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Evolvable Hardware, 2005. Proceedings. 2005 NASA/DoD Conference on

ISSN

1550-6029

Print_ISBN

0-7695-2399-4

Type

conf

DOI

10.1109/EH.2005.6

Filename

1508480