DocumentCode
2003884
Title
Test algorithm for memory cell disturb failures
Author
Aadsen, Duane ; Fenstermaker, Larry ; Higgins, Frank ; Kim, Ilyoung ; Lewandowski, Jim ; Nagy, Jeffrey J.
Author_Institution
Lucent Technol., Bell Labs., USA
fYear
1998
fDate
24-25 Aug 1998
Firstpage
53
Lastpage
56
Abstract
The increasing use of two parted register files (one read port and one write port) has introduced complications in complete, accurate testing. This is especially true when the memories appear as embedded cores in Systems On Chips. In this paper, we describe a new fault effect that has been observed, a basic algorithm for detecting this fault, and enhance a well known classic algorithm for memory testing to detect these faults
Keywords
automatic testing; built-in self test; fault location; integrated circuit testing; integrated memory circuits; embedded cores; fault detection; fault effect; memory cell disturb failures; memory testing; test algorithm; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Decoding; Logic testing; Read-write memory; Registers; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-8494-1
Type
conf
DOI
10.1109/MTDT.1998.705946
Filename
705946
Link To Document