Third-order carrier PLL design and analysis for high dynamic performance

A normal second-order carrier PLL can not meet high dynamic requirement due to the loop bandwidth limitation, it is necessary to take dynamic deviation into the error signal and trade off loop bandwidth for eliminating loop noise required in high dynamic performance. The paper initiate from a second-order carrier PLL model, to design and analyze the dynamic steadiness and the steady state performance of the third-order PLL with INS velocity aiding. As a result of simulation, it finally concludes that the third-order PLL structure with velocity aiding can improve dynamic stress performance.