Title :
Technological parameter and experimental set-up influences on latch-up triggering level in bulk CMOS device
Author :
Dubuc, J.P. ; Azais, B. ; de Murcia, M.
Author_Institution :
DGA/DRET/ETCA/CEG, Centre d´´Etudes de Gramat, France
Abstract :
This paper deals with experimental and simulation results on latch-up triggered by an electrical or X-rays pulse in CMOS/bulk devices. Test condition influences as well as the great importance of process parameters on latch-up immunity are emphasised
Keywords :
CMOS integrated circuits; X-ray effects; carrier lifetime; electrical faults; integrated circuit testing; minority carriers; X-ray pulse; bulk CMOS device; electrical pulse; experimental set-up influences; latch-up triggering level; latchup immunity; process parameters; simulation; technological parameter influences; test condition influences; CMOS technology; Circuit simulation; Circuit testing; Conductivity; Doping profiles; Epitaxial layers; Integrated circuit testing; Life testing; Neutrons; Shape measurement;
Conference_Titel :
Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on
Conference_Location :
St. Malo
Print_ISBN :
0-7803-1793-9
DOI :
10.1109/RADECS.1993.316565
