Title :
Hardening at the design level
Author_Institution :
Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA
Abstract :
The problem of hardening against single event upset in integrated circuits can be considered in terms of charge collected by a given device in a given environment. The author focuses on silicon on epi and silicon on buried insulator (SOI) CMOS digital latched and combinatorial circuits operating in a single event environment
Keywords :
CMOS integrated circuits; circuit reliability; combinatorial circuits; integrated logic circuits; radiation hardening (electronics); semiconductor-insulator boundaries; sequential circuits; silicon; CMOS; SOI; Si; charge collection; combinatorial circuits; latched circuits; radiation hardening; single event environment; single event upset; CMOS digital integrated circuits; Circuit stability; Error analysis; Insulation; Manufacturing; Microelectronics; Photoconductivity; Silicon on insulator technology; Single event upset; Voltage;
Conference_Titel :
Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on
Conference_Location :
St. Malo
Print_ISBN :
0-7803-1793-9
DOI :
10.1109/RADECS.1993.316568
