DocumentCode :
2004670
Title :
Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor
Author :
Papadopoulos, K. ; Papaefstathiou, I.
Author_Institution :
Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Hellas, Greece
fYear :
2008
fDate :
14-15 April 2008
Firstpage :
216
Lastpage :
225
Abstract :
Data compression techniques can alleviate low bandwidth problems in multigigabit networks and are especially useful when combined with encryption. This paper presents a reconfigurable hardware compressor core, the Titan-R, which can compress data streams at 8.5 Gb/sec making it the fastest reconfigurable such device ever proposed. Its compression algorithm is a variation of the most widely used and efficient such scheme the Lempel-Ziv (LZ) algorithm that uses part of the previous input stream as the dictionary. In order to support this high network throughput the Titan-Rutilizes a very fine-grained pipeline and takes advantages of the high-bandwidth provided by the distributed on-chip RAMs of the state-of-the-art FPGAs.
Keywords :
data compression; field programmable gate arrays; multiprocessing systems; pipeline processing; random-access storage; reconfigurable architectures; FPGAs; Lempel-Ziv algorithm; Titan-R; bit rate 8.5 Gbit/s; data compression; multigigabit networks; on-chip RAMs; reconfigurable hardware compressor core; very fine-grained pipeline; Bandwidth; Compression algorithms; Cryptography; Data compression; Dictionaries; Field programmable gate arrays; Hardware; Network-on-a-chip; Pipelines; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on
Conference_Location :
Palo Alto, CA
Print_ISBN :
978-0-7695-3307-0
Type :
conf
DOI :
10.1109/FCCM.2008.14
Filename :
4724904
Link To Document :
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