Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms

In this paper we analyze a dataflow architecture that maps efficiently onto modern FPGA architectures and is composed of communication channels which can be dynamically adapted to the algorithm´s dataflow. The reconfiguration of the architecture´s topology can be achieved within a single clock cycle while DSP operations are in progress. In order to maximize the bandwidth, the dataflow channel width is user- definable and can be chosen based on the application- specific requirements. Furthermore, the dataflow architecture can be efficiently mapped onto multi- FPGA platforms increasing at the same time the overall communication bandwidth.