Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chip

A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90 nm CMOS process. 10x speed ups have been measured on a MP3 playler mapping example.