Title :
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding
Author :
Hoang, Anh Tuan ; Yamazaki, Katsuhiro ; Oyanagi, Shigeru
Author_Institution :
Ritsumeikan Univ., Kusatsu, Japan
Abstract :
This paper describes 3-stage and 4-stage pipeline MD5 implementations on FPGA. This work removes the data dependency of a single step inside the main loop of the MD5 algorithm by data forwarding methodology, and breaks that single step computation into 3/4 pipeline stages. Three implementations on Xilinx Vertex-II are given with the throughput get to 1.04 Gbps, and occupy 1064 hardware slices. Thus, the implementations achieve good tradeoff between hardware size and throughput in comparison with others.
Keywords :
field programmable gate arrays; pipeline processing; 3-stage pipeline; 4-stage pipeline; FPGA; MD5 implementations; Xilinx Vertex-II; data forwarding methodology; multi-stage pipelining; Delay; Equations; Field programmable gate arrays; Frequency; Hardware; Pipeline processing; Registers; Throughput; Data Forwarding; FPGA; MD5; Pipeline;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on
Conference_Location :
Palo Alto, CA
Print_ISBN :
978-0-7695-3307-0
DOI :
10.1109/FCCM.2008.10
