An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects

Current FPGA interconnect networks do not scale well, and use the major part of FPGA area. This has become a bottleneck towards the next-generation FPGAs of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. But to the best of authors´ knowledge, no realization of such an architecture and its design flow has been reported before. In this paper, we develop a novel time-multiplexed FPGA interconnect architecture and its global routing algorithm TMRouter. TMRouter is based on the negotiated congestion delay algorithm. It analyzes whether congestion can be solved by time-sharing a wire segment for several nets in a congested channel. Experiments show that, for 16 MCNC benchmark circuits, their minimum channel widths and critical path delays achieved by the TMRouter are 37.50% - 57.89% and 11.90% in average less than those of the VPR router, respectively.