Evaluation of code generation strategies for scalar replaced codes in fine-grain configurable architectures

Fine-grain configurable architectures such as contemporary fieid-programmable gate-arrays (FPGAs) offer ample opportunities for data reuse through application-specific storage structures, making them an ideal target for memory-intensive image/signal processing computations. In this paper we explore the area and time trade-off in terms of configurable resources and overall wall-clock time of several implementation schemes that exploit opportunities for data reuse using scalar replacement in fine-grain FPGAs. The preliminary results, on a Xilinx Virtex FPGA device, reveal that rotation-based solutions combined with predicated accesses tend to lead to higher-quality designs.