Title :
Efficient Reconfigurable On-Chip Buses for FPGAs
Author :
Koch, Dirk ; Haubelt, Christian ; Teich, Jürgen
Author_Institution :
Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
Abstract :
This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.
Keywords :
field programmable gate arrays; system-on-chip; FPGA-based SoC; bit rate 800 Mbit/s; dynamical integrating hardware modules; master modules; reconfigurable on-chip buses; slave modules; Computer science; Delay; Field programmable gate arrays; Hardware; Reconfigurable logic; Routing; Runtime; System-on-a-chip; Tiles; Wires; SoC; bus; communication; runtime reconfiguration;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on
Conference_Location :
Palo Alto, CA
Print_ISBN :
978-0-7695-3307-0
DOI :
10.1109/FCCM.2008.33
