DocumentCode :
2005101
Title :
Time domain numerical simulation for transient waves on reconfigurable coprocessor platform
Author :
He, Chuan ; Zhao, Wei ; Lu, Mi
Author_Institution :
Texas A&M Univ., College Station, TX, USA
fYear :
2005
fDate :
18-20 April 2005
Firstpage :
127
Lastpage :
136
Abstract :
A successful application-oriented reconfigurable coprocessor design requires not only a powerful FPGA-based computing engine along with suitable hardware architecture, but also an efficient algorithm tailored for this special application. In this paper, we present our hardware architecture and numerical algorithms designed to speedup the time-domain finite-difference simulation of linear wave propagation problems in 2D and 3D space on FPGA-based reconfigurable platforms. Application fields of this work include seismic modeling and migration, computational electromagnetics, aeroacoustics, marine acoustics, to name a few. By writing first-order linear wave equations into second-order form, we halve the number of unknowns and simplify the treatment of parameters. We also adopt higher-order finite-difference (FD) schemes to further reduce the number of unknowns at the cost of increasing floating-point computations per discrete grid point. By doing so, we relief the bandwidth requirements between the FPGA and onboard memories but put more burden on the computing engine to take full advantage of FPGA´s computational potentials. The speed of our design implemented on a Xilinx ML401 Virtex-4 evaluation platform is about 1.5∼4 times faster than a pure software implementation of the same algorithm running on a 3.0 GHz DELL workstation. This impressive result is mainly attributed to the memory architecture design, which is well-tuned for our numerical higher-order FD algorithms and can utilize onboard memory bandwidth more wisely. Furthermore, the good scalability of our design makes it compatible with most commercial reconfigurable coprocessor platforms and correspondingly, the performance would be proportional to their onboard memory bandwidth.
Keywords :
coprocessors; field programmable gate arrays; finite difference time-domain analysis; floating point arithmetic; logic design; memory architecture; reconfigurable architectures; wave equations; wave propagation; FPGA-based computing engine; Xilinx ML401 Virtex-4 evaluation platform; application-oriented reconfigurable coprocessor design; first-order linear wave equation; floating-point computation; hardware architecture; higher-order finite-difference scheme; linear wave propagation; memory architecture design; numerical algorithm; onboard memory bandwidth; time domain numerical simulation; Algorithm design and analysis; Bandwidth; Computational modeling; Computer architecture; Coprocessors; Engines; Field programmable gate arrays; Finite difference methods; Hardware; Numerical simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on
Print_ISBN :
0-7695-2445-1
Type :
conf
DOI :
10.1109/FCCM.2005.65
Filename :
1508533
Link To Document :
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