An Implementation of the Conjugate Gradient Algorithm on FPGAs

The conjugate gradient is a prominent iterative method for solving systems of sparse linear equations. Large-scale scientific applications often utilize a conjugate gradient solver at their computational core. Since a single iteration of a conjugate gradient solver requires a sparse matrix-vector multiply operation it is imperative that this operation be computed efficiently. In this paper we present a field programmable gate array (FPGA) based implementation of a double precision, non-preconditioned, conjugate gradient solver for finite-element or finite-difference methods. We show that our FPGA implementation can outperform current generation processors while running at a ~30X slower clock rate. Our work utilizes the SRC Computers, Inc. MAPStation hardware platform along with the "Carte" software programming environment.