Exploring Well-Configurations for Minimizing Single Event Latchup

This work experimentally studies single event latchup (SEL) prevention by altering well configurations. The well structures under consideration in this paper are ordinary twin-well structure, triple-well structure with deep N-well (DNW) and triple-well structure with deep P-well (DPW). Doping profiles are also varied in our experiments. Neutron irradiation tests for test chips fabricated in 55-nm and 90-nm bulk Si CMOS processes show that SEL can be suppressed with a DPW or a DNW well configuration and a high-dose implantation in the well. Among these, DPW was the most effective to eliminate SEL, and no SEL was observed throughout our irradiation tests in the SRAM with DPW in both 55-nm and 90-nm processes. In addition, DPW brings a desirable side effect of single event upset (SEU) reduction. A disadvantage is a cost to develop a DPW process. DNW is a common process option and hence it is easily adopted for SEL prevention, but we need to pay attention to the fact that DNW increases SEU rate. Increasing well doping in twin-well structure reduced SEL by 60%.