Title :
Address decoder faults and their tests for two-port memories
Author :
Hamdioui, S. ; Van De Goer, A.J.
Author_Institution :
Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Abstract :
A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced, together with the test strategy
Keywords :
decoding; fault diagnosis; integrated circuit testing; integrated memory circuits; address decoder faults; fault modeling; test strategy; two-port memories; Built-in self-test; Circuit faults; Circuit testing; Computer architecture; Decoding; Electrical capacitance tomography; Electronic switching systems; Information technology; Interference; Read-write memory;
Conference_Titel :
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8494-1
DOI :
10.1109/MTDT.1998.705954
