Title :
Flip-flop hardening for space applications
Author :
Monnier, T. ; Roche, F.M. ; Cathebras, G.
Author_Institution :
Lab. d´´Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
The purpose of this work is to design a flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two D-latch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback
Keywords :
circuit feedback; flip-flops; integrated memory circuits; logic design; radiation hardening (electronics); space vehicle electronics; D-latch; design hardening technique; dynamic SEU; flip-flop hardening; flip-flop memory; hardened latch; high impedance state; nMOS feedback; single event upset; space radiation environment; static SEU; Clocks; DH-HEMTs; Digital circuits; Flip-flops; Latches; Logic; MOS devices; Orbital robotics; Pulse generation; Writing;
Conference_Titel :
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8494-1
DOI :
10.1109/MTDT.1998.705955
