Title :
Two step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact-Penetrating Cellplate (SABPEC) for 64MbDRAM STC Cell
Author :
Itob, H. ; Miyagawa, Y. ; Takahashi, M. ; Mitsuhashi, T. ; Kimura, Y. ; Endoh, A. ; Nagatomo, Y. ; Yoshimaru, M. ; Ichikawa, F. ; Ino, M.
Author_Institution :
Oki Electric Industry Co., Japan
Keywords :
Capacitance; Capacitors; Conductivity; Etching; Isolation technology; Rough surfaces; Shape; Surface morphology; Surface resistance; Surface roughness;
Conference_Titel :
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on
Conference_Location :
Oiso, Japan
DOI :
10.1109/VLSIT.1991.705964
