DocumentCode
2006527
Title
Silicon compiler generates fast multipliers embedded in data path
Author
Servant, Jean-Michel ; Delamotte, Pascal ; Keryvel, Georges
Author_Institution
Bull SA, Les Clayes sous Bois, France
fYear
1988
fDate
7-9 June 1988
Firstpage
973
Abstract
The authors introduce a multiplier generator presenting two major novel features: Booth/Wallace multipliers can be embedded in a data path, and a design strategy based on intelligent silicon compilation allows user-directed detailed refinement. This generator produces a smaller, faster, and safer design than an equivalent one manually completed. Moreover, it generates Csa-tree/Booth multipliers embedded in data paths, which has seldom been achieved, especially for big multipliers.<>
Keywords
circuit layout CAD; logic CAD; multiplying circuits; Booth/Wallace multipliers; Csa-tree/Booth multipliers; data path; design strategy; intelligent silicon compilation; multiplier generator; user-directed detailed refinement; Acceleration; CMOS technology; Computer industry; Costs; Delay; Environmental management; Parallel processing; Process design; Refining; Silicon compiler;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15086
Filename
15086
Link To Document