2007035

Full cmos min-sum analog iterative decoder

Hemati, Saied ; Banihashemi, Amir H.

Carleton University

2003

29 June-4 July 2003

347

347

BiCMOS integrated circuits; Bipolar transistors; CMOS analog integrated circuits; CMOS technology; Delay; Iterative algorithms; Iterative decoding; MOSFETs; Parity check codes; Turbo codes;

English

ieee

Information Theory, 2003. Proceedings. IEEE International Symposium on

0-7803-7728-1

conf

10.1109/ISIT.2003.1228362

1228362